Lam Research Kiyo(R) F Series Enables Critical Conductor Etch for Advanced Memory
"For 3D NAND, our customers face significant challenges in addressing difficult etch requirements, meeting aggressive production ramps, and achieving the cost benefits they need to make the transition from planar NAND," said
By stacking memory cells vertically, NAND flash manufacturers can pack more storage capacity onto a smaller device, ease lithography requirements, and reduce manufacturing cost per bit. For multilayer 3D NAND structures, critical conductor etch processes include staircase etch and high aspect ratio (HAR) mask open for vertical channels. This mask open is crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels. For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations.
Building on Lam's market-leading Kiyo conductor etch products, the Kiyo F Series delivers high productivity while minimizing variability for advanced memory applications. Lam's MMP technology provides advanced profile and CD control for vertical profiles with good selectivity and tuning controls for consistent etch depths. These capabilities enable higher trim rate for 3D NAND staircase etch along with excellent repeatability, which is needed for manufacturing environments. Symmetric chamber design and radial tuning provide best-in-class uniformity, which is essential for minimizing CD variability. For new generations of advanced memory as well as logic devices, MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity.
Kiyo F Series has won production and development tool of record positions for critical conductor etch applications at all major memory manufacturers. For 3D NAND, applications include staircase etch and HAR mask open for vertical channel and slit; for DRAM, these include HAR gates, HAR trenches, and metal recess. Because of these wins, the Kiyo F Series installed base has more than tripled in the past 12 months. In addition, due to strong positions at technology inflections, the product is expected to gain significant adoption as next-generation processes move into production.
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Statements made in this press release that are not of historical fact are forward-looking statements and are subject to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements relate to, but are not limited to, statements concerning the capability and performance of Lam's tools, future market share gains, customer challenges, customer collaborations, the effects of tool of record positions on Lam's sales, revenues or market share, and the future adoption or other success of Lam's products. Such forward-looking statements are based on current beliefs and expectations and are subject to risks, uncertainties and changes in condition, significance, value and effect, including those discussed in Lam's annual report on Form 10-K under the heading "Risk Factors" as well as in other documents filed by Lam with the
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