Lam Research Adds Global Wafer Stress Management Solutions to Portfolio for 3D NAND Scaling
While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.
Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.
In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.
“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said
Lam Research Corporation is a global supplier of innovative wafer fabrication equipment and services to the semiconductor industry. As a trusted, collaborative partner to the world’s leading semiconductor companies, we combine superior systems engineering capability, technology leadership, and unwavering commitment to customer success to accelerate innovation through enhanced device performance. In fact, today, nearly every advanced chip is built with Lam technology.
Caution Regarding Forward-Looking Statements
Statements made in this press release that are not of historical fact are forward-looking statements and are subject to the safe harbor provisions created by the Private Securities Litigation Reform Act of 1995. Such forward-looking statements relate to, but are not limited to the performance of the tools we sell; the requirements of our customers for 3D NAND scaling as well as other applications; the key enablers to 3D NAND scaling; the requirements for stress management on wafers, die and features; and the cost effectiveness of our tools offerings, as well as the other risks and uncertainties that are described in the documents filed or furnished by us with the Securities and Exchange Commission, including specifically the Risk Factors described in our annual report on Form 10-K for the fiscal year ended June 24, 2018 and our quarterly reports on Form 10-Q for the fiscal quarters ended
Source: Lam Research Corporation